I've been working on this new project to expand an old project done a couple of years ago because there's so much going on within this design. It makes telling the story more interesting and it emphasizes what you can do in software. So what am I talking about? Linear Feedback Shift Registers. Great, what's that?

Simply put, a LFSR is a normal shift register where certain Q outputs are wrapped back the the starting bit via XOR logic gates to follow a polynomial equation that maximizes the number of random bits streamed from the final stage of the shift register. In my example, I used a 24 bit LFSR that follows X^24 + X^23 + X^22 + x^17 + 1 polymomial and produces 16,777,215 pseudo-random bits before repeating the sequence verses just 24 before repeating if the output was wrapped to the input without the XOR feedback. So you can see there is a fantastic increase in a random looking output. If you add more bit positions in a long LFSR, the count really takes off. So what, you say.

If you have a long sequence of randomized bits in a stream going through a XOR gate with the other input jamset to logic LOW, the stream appears to be non-sense to a receiving party. Then you take the second input to the gate and apply a message bit stream. The output still appears to be random but has been encrypted with your message. If the receive now also has an XOR gate and inputs this stream with a second stream from an identical LFSR sync'd up with the sender, two things are relevant here. First while both streams match, nothing appears from the logic gate output because there is no exclusive bits when both input are the same. When the message bits come along, they produce exclusive bits that appear at the output. Then the stream continues to match and the gate output goes silent again. Cool, encryption takes place quietly and efficiently and no one is the wiser who might be listening in.

There are several useful conclusions that come from this type of design. First of all, it's a field-day for mathmaticians. There is a lot more creative concepts that have been derived from this like cyclic redundancy checks. I leave that research up to you. You could write books on this subject and many already have been written. I just wanted to build enough of a LFSR to make it into a hobby project to fiddle around with.

Other things to realize is usually this sort of thing is done in software. Crazy, lengthy mathmatical operations are best done there - right? First, yes this sort of appoach can be easily done in software but at a price. It's processor intensive where when done in hardware is easy to construct and takes care of its self without loading down a processor. You need the processor to manipulate the LFSR and control the I/O of your data messages.

So check out the project section for the results of my playing with a 24-bit LFSR with a 3-byte seed loader to vary the stream dynamics. This is the improvement I made over the earlier project.